Semiconductor memory devices, including flash memory, typically utilize memory cells to store data as an electrical value, such as an electrical charge or voltage. A flash memory cell, for example, includes a single transistor with a floating gate that is used to store a charge representative of a data value. Flash memory is a non-volatile data storage device that can be electrically erased and reprogrammed. More generally, non-volatile memory (e.g., flash memory, as well as other types of non-volatile memory implemented using any of a variety of technologies) retains stored information even when not powered, as opposed to volatile memory, which requires power to maintain the stored information. Increases in storage density have been facilitated in various ways, including increasing the density of memory cells on a chip enabled by manufacturing developments, and transitioning from single-level flash memory cells to multi-level flash memory cells, so that two or more bits can be stored by each flash memory cell. For example, a multi-level cell (MLC) NAND flash typically has four possible states per cell, yielding two bits of information per cell. Further, a MLC NAND has two page types: (1) a fast page (sometimes called lower page), and (2) a slow page (sometimes called upper page).
A drawback of increasing storage density is that the stored data is increasingly prone to being stored and/or read erroneously. Further, as a memory device is used, program-erase cycles (PE cycles) wear the memory device and cause it to have less ideal charge distributions, causing bit errors on reads. An error control coding (ECC) engine is utilized to limit the number of uncorrectable errors that are introduced by electrical fluctuations, defects in the storage medium, operating conditions, device history, and/or write-read circuitry, etc. However, relying solely on ECC to manage bit errors may not maximize the life of the memory device.